CDC5801ADBQ Datasheet, PDF (5/18 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†
Supply voltage range, V_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Output voltage range, V_O, at any output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_DD + 0.5 V
Input voltage range,V_I, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_DD + 0.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 85°C
POWER RATING
DBQ
1400 mW
11 mW/°C
740 mW
‡ _{This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with}
no air flow.
recommended operating conditions
Supply voltage, VDD (VDDP, VDDPA, VDDO)
High-level input voltage, VIH (CMOS)
Low-level input voltage, VIL (CMOS)
REFCLK low-level input voltage, VIL
REFCLK high-level input voltage, VIH
Input signal low voltage, VIL (STOPB, DLYCTRL, LEADLAG)
Input signal high voltage, VIH (STOPB, DLYCTRL, LEADLAG)
Input reference voltage for (REFCLK) (VDDREF)
Input reference voltage for (DLYCTRL and LEADLAG) (VDDPD)
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
MIN
3
0.7 × VDD
0.7 × VDDREF
0.7 × VDDPD
1.235
1.235
−40
NOM
3.3
MAX
3.6
0.3 × VDD
0.3 × VDDREF
0.3 × VDDPD
VDD
VDD
−16
16
85
UNIT
V
V
V
V
V
V
V
V
V
mA
mA
°C
timing requirements
Input frequency of modulation, fmod (if driven by SSC CLKIN)
Modulation index (nonlinear maximum 0.5%)
Input slew rate, SR
Input duty cycle on REFCLK
Input frequency on REFCLK
Allowable frequency on DLYCTRL
Allowable frequency on LEADLAG
Allowable duty cycle on DLYCTRL and LEADLAG
MIN
1
40%
19
25%
MAX
33
0.6%
4
60%
125
200
400
75%
UNIT
kHz
V/ns
MHz
MHz
MHz
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