CDC5801ADBQ Datasheet, PDF (10/18 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
state transition latency specifications
PARAMETER
t(powerup)
Delay time, PWRDNB↑ to CLKOUT/
CLKOUTB output settled (excluding
t(DISTLOCK))
Delay time, PWRDNB↑ to internal PLL and
clock are on and settled
t(V_DDpowerup)
Delay time, power up to CLKOUT/CLKOUTB
output settled
Delay time, power up to internal PLL and
clock are on and settled
t(MULT)
t(CLKON)
MULT0 and MULT1 change to CLKOUT/
CLKOUTB output resettled (excluding
t(DISTLOCK))
STOPB↑ to CLKOUT/CLKOUTB glitch-free
clock edges
t(CLKSETL)
STOPB↑ to CLKOUT/CLKOUTB output
settled to within 50 ps of the phase before
STOPB was disabled
t(CLKOFF)
STOPB↓ to CLKOUT/CLKOUTB output dis-
abled
t(powerdown)
Delay time, PWRDNB↓ to the device in the
power-down mode
t(STOP)
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode (STOPB = 1)
t(ON)
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
† _{All typical values are at VDD = 3.3 V, TA = 25°C.}
FROM
TO
TEST
CONDITIONS
Powerdown Normal See Figure 6
VDD
Normal See Figure 6
Normal Normal See Figure 7
CLK Stop Normal See Figure 8
CLK Stop Normal See Figure 8
Normal
Normal
STOPB
Normal
CLK
Stop
See Figure 8
Power−
down
See Figure 6
Normal See Figure 8
CLK
stop
See Figure 8
MIN TYP† MAX UNIT
3
ms
3
3
ms
3
1 ms
10 ns
20 cycles
5 ns
1 ms
100 µs
100
ms
PARAMETER MEASUREMENT INFORMATION
CLKOUT
CLKOUTB
VCM
50 Ω
50 Ω
10 pF
Figure 1. Test Load and Voltage Definitions (V_O(STOP), V_OX, V_OH, V_OL)
10
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