CDC351DBR Datasheet, PDF (5/13 Pages) Texas Instruments – 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

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From Output
Under Test
C_L = 50 pF
(see Note A)
CDC351. CDC351I
1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003
500 Ω
500 Ω
6V
S1
Open
GND
TEST
t_PLH /t_PHL
t_PLZ /t_PZL
t_PHZ /t_PZH
S1
Open
6V
GND
Timing Input
LOAD CIRCUIT
1.5 V
t_w
Input 1.5 V
3V
3V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
Data Input
t_su
t_h
1.5 V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
Input
t_PLH
1.5 V
Output
2V
0.8 V
t_r
1.5 V
2V
1.5 V
t_f
3V
0V
t_PHL
V_OH
0.8 V _VOL
Output
Control
(low-level
enabling)
t_PZL
Output
Waveform 1
S1 at 6 V
(see Note B)
t_PZH
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t_PLZ
1.5 V
t_PHZ
1.5 V
3V
1.5 V
0V
3V
V_OL + 0.3 V
V_OL
V_OH
V_OH - 0.3 V
≈0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r≤ 2.5 ns,
t_f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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