CD74HC42 Datasheet, PDF (5/6 Pages) Texas Instruments – High Speed CMOS Logic BCD To Decimal Decoder 1 of 10

CD74HC42, CD74HCT42
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
Power Dissipation Capacitance C_PD
-
(Notes 4, 5)
5
-
65
-
-40^oC TO
85^oC
MIN MAX
-
-
-55^oC TO
125^oC
MIN MAX UNITS
-
-
pF
HCT TYPES
Propagation Delay,
Input to Y (Figure 2)
t_PLH, t_PHL C_L = 50pF
4.5
-
-
35
-
44
-
53
ns
Any Input to Y
Output Transition Time
(Figure 2)
t_PLH, t_PHL C_L = 15pF
5
t_TLH, t_THL C_L = 50pF
4.5
-
14
-
-
-
-
-
-
15
-
19
-
-
ns
22
ns
Input Capacitance
C_IN
-
Power Dissipation Capacitance C_PD
-
(Notes 4, 5)
-
-
-
10
-
10
-
10
pF
5
-
70
-
-
-
-
-
pF
NOTES:
4. C_PD is used to determine the dynamic power consumption, per package.
5. P_D = V_CC2 f_i (C_PD + C_L) where: f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5