CD74HC42 Datasheet, PDF (1/6 Pages) Texas Instruments – High Speed CMOS Logic BCD To Decimal Decoder 1 of 10

Data sheet acquired from Harris Semiconductor
SCHS133
August 1997
CD74HC42,
CD74HCT42
High Speed CMOS Logic
BCD To Decimal Decoder (1 of 10)
[ /Title
(CD74H
C42,
CD74H
CT42)
/Subject
(High
Speed
CMOS
Logic
BCD To
Deci-
Features
Description
• Buffered Inputs and Outputs
•
Typical Propagation Delay:
C_L = 15pF, T_A = 25^oC
12ns
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
The Harris CD74HC42, CH74HCT42 BCD-to-Decimal
Decoders utilize silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL decoders with the low
power consumption of standard CMOS integrated circuits.
These devices have the capability of driving 10 LSTLL loads
and are compatible with the standard 74LS logic family. One
of ten outputs (low on select) is selected in accordance with
the BCD input. Non-valid BCD inputs result in none of the
outputs being selected (all outputs are high).
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Ordering Information
PART NUMBER TEMP. RANGE (^oC) PACKAGE
PKG.
NO.
CD74HC42E
-55 to 125
16 Ld PDIP E16.3
CD74HCT42E
-55 to 125
16 Ld PDIP E16.3
CD74HC42M
-55 to 125
16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC42, CD74HCT42
(PDIP, SOIC)
TOP VIEW
Y0 1
Y1 2
Y2 3
Y3 4
Y4 5
Y5 6
Y6 7
GND 8
16 V_CC
15 A0
14 A1
13 A2
12 A3
11 Y9
10 Y8
9 Y7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1689.1