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CD74HC154 Datasheet, PDF (5/6 Pages) Texas Instruments – High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer
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CD74HC154, CD74HCT154
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
E2 to Output
TEST
25oC
SYMBOL CONDITIONS VCC (V) MIN TYP MAX
tPLH, tPHL CL = 50pF
2
-
- 175
4.5
-
-
35
-40oC TO
85oC
-55oC TO 125oC
MIN MAX MIN MAX UNITS
-
220
-
265 ns
-
44
-
53
ns
Output Transition Time
(Figure 1)
CL =15pF
CL = 50pF
tTLH, tTHL CL = 50pF
5
-
14
-
-
-
-
-
ns
6
-
-
30
-
37
-
45
ns
2
-
-
75
-
95
-
110 ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
CIN
-
Power Dissipation Capacitance CPD
-
(Notes 4, 5)
-
-
-
10
-
10
-
10
pF
5
-
88
-
-
-
-
-
pF
HCT TYPES
Propagation Delay (Figure 2)
Address to Output
tPLH, tPHL
CL = 50pF
CL =15pF
E1 to Output
tPLH, tPHL CL = 50pF
CL =15pF
E2 to Output
tPLH, tPHL CL = 50pF
CL =15pF
Output Transition Time
tTLH, tTHL CL = 50pF
Input Capacitance
CIN
-
Power Dissipation Capacitance CPD
-
(Notes 4, 5)
4.5
-
-
35
-
44
-
5
-
14
-
-
-
4.5
-
-
34
-
43
-
5
-
14
-
-
-
-
4.5
-
34
-
43
-
5
-
14
-
-
-
-
4.5
-
-
15
-
19
-
-
-
-
10
-
10
-
5
84
-
-
-
-
53
ns
-
ns
51
ns
-
ns
51
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per gate.
5. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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