CD54HC32_07 Datasheet, PDF (5/13 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input OR Gate

CD54HC32, CD74HC32, CD54HCT, CD74HCT32
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_I
C_PD
-
-
-
-
10
-
10
-
10
pF
-
5
- 22 -
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
t_RHL, t_PHL C_L = 50pF
4.5 -
-
24
-
30
-
36
ns
Output (Figure 2)
Propagation Delay, Data Input to t_PLH, t_PHL C_L = 15pF
5
-9
-
-
-
-
-
ns
Output Y
Transition Times (Figure 2)
t_TLH, t_THL C_L = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
C_I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C_PD
-
5
- 22 -
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per gate.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5