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CD54HC10_06 Datasheet, PDF (5/11 Pages) Texas Instruments – High-Speed CMOS Logic Triple 3-Input NAND Gate
◁
CD54HC10, CD74HC10, CD54HCT10, CD74HCT10
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
2
-
- 75
-
95
-
110
ns
4.5 -
-
15
-
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
CI
CPD
-
-
-
-
10
-
10
-
10
pF
-
5
- 24 -
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
tPLH, tPHL CL = 50pF
4.5 -
-
24
-
30
-
36
ns
Output (Figure 2)
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5
-9
-
-
-
-
-
ns
Output Y
Transition Times (Figure 2)
tTLH, tTHL CL = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
- 28 -
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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