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CD54HC10_06 Datasheet, PDF (1/11 Pages) Texas Instruments – High-Speed CMOS Logic Triple 3-Input NAND Gate
Data sheet acquired from Harris Semiconductor
SCHS128C
August 1997 - Revised September 2003
CD54HC10, CD74HC10,
CD54HCT10, CD74HCT10
High-Speed CMOS Logic
Triple 3-Input NAND Gate
[ /Title
(CD74
HC10,
CD74
HCT10
)
/Sub-
ject
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
Harris
Semi-
Features
Description
• Buffered Inputs
•
Typical Propagation Delay:
CL = 15pF, TA = 25oC
8ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC10 and ’HCT10 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
Ordering Information
PART NUMBER
CD54HC10F3A
CD54HCT10F3A
CD74HC10E
CD74HC10M
CD74HC10MT
CD74HC10M96
CD74HCT10E
CD74HCT10M
CD74HCT10MT
TEMP. RANGE
(oC)
PACKAGE
-55 to 125 14 Ld CERDIP
-55 to 125 14 Ld CERDIP
-55 to 125 14 Ld PDIP
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld PDIP
-55 to 125 14 Ld SOIC
-55 to 125 14 Ld SOIC
CD74HCT10M96
-55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC10, CD54HCT10
(CERDIP)
CD74HC10, CD74HCT10
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1