CD54HC03 Datasheet, PDF (5/9 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Power Dissipation Capacitance
(Notes 5, 6)
C_PD
-
5
-9
-
-
-
-
-
pF
NOTES:
5. C_PD is used to determine the dynamic power consumption, per gate.
6. P_D = C_PD V_CC2 f_i + Σ (C_L V_CC2 f_o) + Σ (V_L2/R_L) (Duty Factor “Low”)
where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC = supply voltage, Duty Factor “Low” = percent of
time output is “low”, V_L = output voltage, R_L = pull-up resistor.
Test Circuits and Waveforms
V_S
t_PLZ
nY
OUTPUT
LOW
nA(nB)
nB(nA)
V_CC
INPUT LEVEL
V_S
90%
10%
t_THL
OUTPUT
OFF
OPEN
DRAIN
NAND
GATE
t_PZL
V_OH
V_OL
OUTPUT
LOW
1kΩ
V_CC
50pF
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY
TIMES, AND TEST CIRCUIT
800
V_L
0.8V (HCT V_IL MAX)
700
≤ 1.35V (HC V_IL MAX)
R_L
0.26V
600
V_O ^{RON MAX =} 4mA ⁼
R_ON
65Ω AT 25^oC
500
400
300
V_CC = 5V V_L
±10%
200
R_L
HC/HCT03
100
V_O
HCT
HC
0 1 2 3 4 5 6 7 8 9 10
V_L, LOAD VOLTAGE (V)
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5