|
CD54HC03 Datasheet, PDF (4/9 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain | |||
|
◁ |
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
DC Electrical Speciï¬cations (Continued)
PARAMETER
Low Level Output
Voltage CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
TEST
CONDITIONS
25oC
SYMBOL
VOL
VI (V)
VIH or
VIL
IO (mA) VCC (V) MIN
0.02
4.5
-
4
4.5
-
TYP MAX
- 0.1
- 0.26
II
VCC
-
and
GND
ICC
VCC or
0
GND
âICC
VCC
-
(Note 4) - 2.1
5.5
-
±0.1
5.5
-
-
2
4.5 to - 100 360
5.5
-40oC TO 85oC
MIN MAX
-
0.1
-
0.33
-
±1
-
20
-
450
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
-55oC TO 125oC
MIN MAX UNITS
-
0.1
V
-
0.4
V
-
±1
µA
-
40
µA
-
490
µA
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nB
1
NOTE: Unit Load is âICC limit
tions table, e.g., 360µA max at
speciï¬ed
25oC.
in
DC
Electrical
Speciï¬ca-
Switching Speciï¬cations Input tr, tf = 6ns
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
tPLH, tPHL CL = 50pF
2
-
- 100
-
125
-
150
ns
4.5 -
-
20
-
25
-
30
ns
6
-
- 17
-
21
-
26
ns
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5
-8
-
-
-
-
-
ns
Output Y
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
2
-
- 75
-
4.5 -
-
15
-
95
18
110
ns
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
CI
CPD
-
-
-
-
10
-
10
-
10
pF
-
5
- 6.4 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Input to Output (Figure 1)
tPLH, tPHL CL = 50pF
4.5 -
-
24
-
30
-
36
ns
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5
-9
-
-
-
-
-
ns
Output Y
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
4
|
▷ |