CD54AC109_08 Datasheet, PDF (5/15 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, after CLK↑
trec
Recovery time, before CLK↑
CLK high or low
CLR or PRE
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
71
7
6.3
7.7
0
3.5
–40°C to
85°C
MIN MAX
81
6
5.5
6.8
0
3.1
UNIT
MHz
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, after CLK↑
trec
Recovery time, before CLK↑
CLK high or low
CLR or PRE
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
100
5
4.5
5.5
0
2.5
–40°C to
85°C
MIN MAX
114
4.4
3.9
4.8
0
2.2
UNIT
MHz
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 1.5 V, C_L = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN MAX
–40°C to
85°C
MIN MAX
fmax
tPLH
CLK
CLR or PRE
Q or Q
8
129
153
9
117
139
tPHL
CLK
CLR or PRE
Q or Q
129
117
153
139
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 3.3 V ± 0.3 V, C_L = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN MAX
–40°C to
85°C
MIN MAX
fmax
tPLH
CLK
CLR or PRE
Q or Q
71
3.6 14.4
4.3 17.1
81
3.7 13.1
4.4 15.5
tPHL
CLK
CLR or PRE
Q or Q
3.6 14.4
4.3 17.1
3.7 13.1
4.4 15.5
UNIT
MHz
ns
ns
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