CD54AC109_08 Datasheet, PDF (2/15 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H^†
H^†
H
H
↑
L
L
L
H
H
H
↑
H
L
Toggle
H
H
↑
L
H
Q0 Q0
H
H
↑
H
H
H
L
H
H
L
X
X
Q0 Q0
† _{Unpredictable and unstable condition if both PRE and CLR}
go low simultaneously
logic diagram, each flip-flop (positive logic)
PRE
J
C
C
K
CLK
TG
Q
TG
C
C
C
TG
C
C
C
TG
CLR
C
C
Q
2
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