CD5474HC11 Datasheet, PDF (5/6 Pages) Texas Instruments – High Speed CMOS Logic Triple 3-Input AND Gate

CD54/74HC11, CD54/74HCT11
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Transition Times (Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
- 75
-
95
-
110
ns
4.5 -
-
15
-
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
C_I
C_L = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
C_PD
C_L = 15pF
5
- 26 -
-
-
-
-
pF
(Notes 5, 6)
HCT TYPES
Propagation Delay, Input to
t_PLH, t_PHL C_L = 50pF
4.5 -
-
28
-
35
-
42
ns
Output (Figure 2)
Propagation Delay, Data Input to t_PLH, t_PHL C_L = 15pF
5
- 11 -
-
-
-
-
ns
Output Y
Transition Times (Figure 2)
t_TLH, t_THL C_L = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
C_I
C_L = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 5, 6)
C_PD
-
5
- 28 -
-
-
-
-
pF
NOTES:
5. C_PD is used to determine the dynamic power consumption, per gate.
6. P_D = V_CC2 f_i (C_PD + C_L) where f_i = input frequency, C_L = output load capacitance, V_CC = supply voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5