CD54-74HC4514 Datasheet, PDF (5/14 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES

CD54HC4514, CD74HC4514, CD74HC4515
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns (Continued)
PARAMETER
E to Outputs
TEST
SYMBOL CONDITIONS V_CC (V) MIN
t_PHL, t_PLH C_L = 50pF
2
-
4.5
-
25^oC
TYP MAX
- 175
-
35
-40^oC TO
85^oC
MIN MAX
-
220
-
44
-55^oC TO
125^oC
MIN MAX UNITS
-
265 ns
-
53
ns
Output Transition Time
C_L = 15pF
5
-
14
-
-
-
-
-
ns
C_L = 50pF
6
-
-
30
-
37
-
45
ns
t_THL, t_TLH C_L = 50pF
2
-
-
75
-
95
-
110 ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_IN
C_PD
C_L = 50pF
-
-
10
-
10
-
10
-
5
-
70
-
-
-
-
10
pF
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_rC_L
CLOCK
90%
10%
t_fC_L
50%
10%
t_WL
t_WL
+
t_WH
=
I
fC_L
50%
50%
t_WH
V_CC
GND
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
90%
50%
10%
INVERTING
OUTPUT
t_PHL
t_f = 6ns
V_CC
GND
t_TLH
90%
50%
10%
t_PLH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
5