TLV320AIC27 Datasheet, PDF (48/52 Pages) Texas Instruments – STEREO AUDIO CODEC

TLV320AIC27
STEREO AUDIO CODEC
SLAS253 – MARCH 2000
detailed timing diagrams, AV_DD = 5 V, DV_DD = 3.3 V, GND = 0 V, T_A = 0°C to 70°C (unless otherwise
stated) (continued)
tsu
BIT_CLK
th
SYNC
SDATA_OUT
PARAMETER
MIN
tsu Setup to falling edge of BIT_CLK
15
th
Hold from falling edge of BIT_CLK
5
NOTE: Setup and hold time parameters for SDATA_IN are with respect to AC’97 controller.
Figure 19. Data Setup and Hold (50 pF external load)
TYP MAX UNIT
ns
ns
BIT_CLK
tr(CLK)
tf(CLK)
tr(SYNC)
SYNC
tf(SYNC)
SDATA_IN
tr(DIN)
tf(DIN)
tr(DOUT)
SDATA_OUT
tf(DOUT)
tr(CLK)
tf(CLK)
tr(SYNC)
tf(SYNC)
tr(DIN)
tf(DIN)
tr(DOUT)
tf(DOUT)
BIT_CLK rise time
BIT_CLK fall time
SYNC rise time
SYNC fall time
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
PARAMETER
MIN TYP MAX UNIT
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
Figure 20. Signal Rise and Fall Times (50-pF external load)
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