AFE5805_1 Datasheet, PDF (48/51 Pages) Texas Instruments – FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel

AFE5805
SBOS421C – MARCH 2008 – REVISED OCTOBER 2008................................................................................................................................................. www.ti.com
GROUNDING AND BYPASSING
The AFE5805 distinguishes between three different
grounds: AVSS1 and AVSS2 (analog grounds), and
LVSS (digital ground). In most cases, it should be
adequate to lay out the printed circuit board (PCB) to
use a single ground plane for the AFE5805. Care
should be taken that this ground plane is properly
partitioned between various sections within the
system to minimize interactions between analog and
digital circuitry. Alternatively, the digital (LVDS)
supply set consisting of the LVDD and LVSS pins can
be placed on separate power and ground planes. For
this configuration, the AVSS and LVSS grounds
should be tied together at the power connector in a
star layout.
All bypassing and power supplies for the AFE5805
should be referenced to this analog ground plane. All
supply pins should be bypassed with 0.1µF ceramic
chip capacitors (size 0603 or smaller). In order to
minimize the lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, these capacitors are best placed
directly under the package. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF, effective at
lower frequencies) may also be used on the main
supply pins. These components can be placed on the
PCB in proximity (< 0.5in or 12.7mm) to the AFE5805
itself.
The AFE5805 internally generates a number of
reference voltages, such as the bias voltages (VB1
through VB6). Note that in order to achieve optimal
low-noise performance, the VB1 pin must be
bypassed with a capacitor value of at least 1µF; the
recommended value for this bypass capacitor is
2.2µF. All other designed reference pins can be
bypassed with smaller capacitor values, typically
0.1µF. For best results choose low-inductance
ceramic chip capacitors (size 402) and place them as
close as possible to the device pins as possible.
High-speed mixed signal devices are sensitive to
various types of noise coupling. One primary source
of noise is the switching noise from the serializer and
the output buffer/drivers. For the AFE5805, care has
been taken to ensure that the interaction between the
analog and digital supplies within the device is kept to
a minimal amount. The extent of noise coupled and
transmitted from the digital and analog sections
depends on the effective inductances of each of the
supply and ground connections. Smaller effective
inductance of the supply and ground pins leads to
improved noise suppression. For this reason, multiple
pins are used to connect each supply and ground
sets. It is important to maintain low inductance
properties throughout the design of the PCB layout by
use of proper planes and layer thickness.
BOARD LAYOUT
Proper grounding and bypassing, short lead length,
and the use of ground and power-supply planes are
particularly important for high-frequency designs.
Achieving optimum performance with a
high-performance device such as the AFE5805
requires careful attention to the PCB layout to
minimize the effects of board parasitics and optimize
component placement. A multilayer PCB usually
ensures best results and allows convenient
component placement.
In order to maintain proper LVDS timing, all LVDS
traces should follow a controlled impedance design
(for example, 100Ω differential). In addition, all LVDS
trace lengths should be equal and symmetrical; it is
recommended to keep trace length variations less
than 150mil (0.150in or 3.81mm).
Additional details on PCB layout techniques can be
found in the Texas Instruments Application Report
MicroStar BGA Packaging Reference Guide
(SSYZ015B), which can be downloaded from the TI
web site (www.ti.com).
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