TMS320C6205_15 Datasheet, PDF (47/73 Pages) Texas Instruments – FIXED-POINT DIGTAL SIGNAL PROCESSOR

TMS320C6205
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
HOLD/HOLDA TIMING
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
timing requirements for the HOLD/HOLDA cycles^† (see Figure 27)
NO.
3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
−200
MIN MAX
P
UNIT
ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles^†‡
(see Figure 27)
NO.
PARAMETER
−200
UNIT
MIN MAX
1 td(HOLDL-EMHZ)
Delay time, HOLD low to EMIF Bus high impedance
4P
§ _ns
2 td(EMHZ-HOLDAL)
Delay time, EMIF Bus high impedance to HOLDA low
0 2P ns
4 td(HOLDH-EMLZ)
Delay time, HOLD high to EMIF Bus low impedance
3P 7P ns
5 td(EMLZ-HOLDAH)
Delay time, EMIF Bus low impedance to HOLDA high
0 2P ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.}
§ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with}
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus†
1
C6205
4
C6205
† _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.}
Figure 27. HOLD/HOLDA Timing
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