TMS320C6205_15 Datasheet, PDF (38/73 Pages) Texas Instruments – FIXED-POINT DIGTAL SIGNAL PROCESSOR

TMS320C6205
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles^{†‡§¶} (see Figure 15 − Figure 18)
−200
NO.
UNIT
MIN
MAX
3 tsu(EDV-AREH)
Setup time, EDx valid before ARE high
4 th(AREH-EDV)
Hold time, EDx valid after ARE high
6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low
7 th(AREL-ARDYH) Hold time, ARDY high after ARE low
1.5
ns
3.5
ns
−[(RST − 3) * P − 6]
ns
(RST − 3) * P + 3
ns
9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low
10 th(AREL-ARDYL) Hold time, ARDY low after ARE low
−[(RST − 3) * P − 6]
ns
(RST − 3) * P + 3
ns
11 tw(ARDYH)
Pulse width, ARDY high
2P
ns
15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low
16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low
−[(WST − 3) * P − 6]
ns
(WST − 3) * P + 3
ns
18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low
−[(WST − 3) * P − 6]
ns
19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low
(WST − 3) * P + 3
ns
† _{To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold}
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡ _{RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are}
programmed via the EMIF CE space control registers.
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
¶ _{The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.}
switching characteristics over recommended operating conditions for asynchronous memory
cycles^{‡§¶#} (see Figure 15 − Figure 18)
NO.
PARAMETER
−200
UNIT
MIN
TYP
MAX
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low
RS * P − 2
ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid
RH * P − 2
ns
5 tw(AREL)
Pulse width, ARE low
RST * P
ns
8 td(ARDYH-AREH) Delay time, ARDY high to ARE high
12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low
13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid
14 tw(AWEL)
Pulse width, AWE low
3P
4P + 5
ns
WS * P − 2
ns
WH * P − 2
ns
WST * P
ns
17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high
3P
4P + 5 ns
‡ _{RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are}
programmed via the EMIF CE space control registers.
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
¶ _{The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.}
# _{Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional}
7P ns following the end of the cycle.
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