TLC320AC02C Datasheet, PDF (47/84 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

3.6 Timing Requirements and Specifications in Master Mode
3.6.1 Recommended Input Timing Requirements for Master Mode, V_DD = 5 V
MIN NOM MAX
tr(MCLK)
tf(MCLK)
Master clock rise time
Master clock fall time
Master clock duty cycle
40%
5
5
60%
tw(RESET)
tsu(DIN)
th(DIN)
RESET pulse duration
DIN setup time before SCLK low (see Figure 4–2)
DIN hold time after SCLK low (see Figure 4–2)
1 MCLK
25
20
UNIT
ns
ns
ns
ns
3.6.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V_DD = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN TYP† MAX UNIT
tf(SCLK)
tr(SCLK)
Shift clock fall time (see Figure 4–2)
Shift clock rise time (see Figure 4–2)
Shift clock duty cycle
45%
13
18 ns
13
18 ns
55%
td(CH-FL)
Delay time from SCLK high to FSD low
(see Figures 4–2 and 4–4 and Note 24)
5
20 ns
td(CH-FH)
td(CH-DOUT)
Delay time from SCLK high to FS high (see Figure 4–2)
Delay time from SCLK high to DOUT valid
(see Figures 4–2 and 4–7)
5
20 ns
20 ns
td(CH-DOUTZ)
Delay time from SCLK↑ to DOUT in high-impedance state
(see Figure 4–8)
20
ns
td(ML-EL)
td(ML-EH)
tf(EL)
tr(EH)
Delay time from MCLK low to EOC low (see Figure 4–9)
Delay time from MCLK low to EOC high (see Figure 4–9)
EOC fall time (see Figure 4–9)
EOC rise time (see Figure 4–9)
40
ns
40
ns
13
ns
13
ns
td(MH-CH)
Delay time from MCLK high to SCLK high
50 ns
td(MH-CL)
Delay time from MCLK high to SCLK low
50 ns
† _{All typical values are at VDD = 5 V and TA = 25°C.}
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
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