TLC320AC02C Datasheet, PDF (12/84 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

1.4 Terminal Functions
TERMINAL
NAME
NO.† NO.‡ ^I/O
DESCRIPTION
ADC VDD
24 32
I Analog supply voltage for the ADC channel
ADC VMID 23 30 O Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be
buffered when used as an external reference.
ADC GND 22 27 I Analog ground for the ADC channel
AUX IN +
28 38 I Noninverting input to auxiliary analog input amplifier
AUX IN –
27 37 I Inverting input to auxiliary analog input amplifier
DAC VDD
DAC VMID
5 49 I Digital supply voltage for the DAC channel
6 51 O Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be
buffered when used as an external reference.
DAC GND
7 54 I Analog ground for the DAC channel
DIN
10
1 I Data input. DIN receives the DAC input data and command information and is
synchronized with SCLK.
DOUT
11
3 O Data output. DOUT outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.
DGTL VDD 9 59
DGTL GND 20 22
I Digital supply voltage for control logic
I Digital ground for control logic
EOC
19 17 O End-of-conversion output. EOC goes high at the start of the ADC conversion
period and low when conversion is complete. EOC remains low until the next ADC
conversion period begins and indicates the internal device conversion period.
FC0
15 11 I Hardware control input. FC0 is used in conjunction with FC1 to request secondary
communication and phase adjustments. FC0 should be tied low if it is not used.
FC1
16 12 I Hardware control input. FC1 is used in conjunction with FC0 to request secondary
communication and phase adjustments. FC1 should be tied low if it is not used.
FS
12
4 I/O Frame synchronization. When FS goes low, DIN begins receiving data bits and
DOUT begins transmitting data bits. In master mode, FS is low during the
simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is
externally generated and must be low for one shift-clock period minimum to initiate
the data transfer.
FSD
17 14 O Frame-synchronization delayed output. This active-low output synchronizes a
slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.
IN +
26 36 I Noninverting input to analog input amplifier
IN –
25 35 I Inverting input to analog input amplifier
MCLK
14 10 I The master-clock input drives all the key logic signals of the AIC.
MON OUT
1 40 O The monitor output allows monitoring of analog input and is a high-impedance
output.
M/S
18 16 I Master/slave select input. When M/S is high, the device is the master and when
low, it is a slave.
† _{Terminal numbers shown are for the FN package.}
‡ _{Terminal numbers shown are for the PM package.}
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