ADC08D1520QML-SP Datasheet, PDF (46/59 Pages) Texas Instruments – ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

ADC08D1520QML-SP
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
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When selecting a balun, it is important to understand the input architecture of the ADC. There are specific balun
parameters of which the system designer should be mindful. A designer should match the impedance of the
analog source to the ADC08D1520’s on-chip 100Ω differential input termination resistor. The range of this input
termination resistor is described in the Converter Electrical Characteristics as the specification R_IN.
Also, the phase and amplitude balance are important. The lowest possible phase and amplitude imbalance is
desired when selecting a balun. The phase imbalance should be no more than ±2.5° and the amplitude
imbalance should be limited to less than 1dB at the desired input frequency range.
Finally, when selecting a balun, the VSWR (Voltage Standing Wave Ratio), bandwidth and insertion loss of the
balun should also be considered. The VSWR aids in determining the overall transmission line termination
capability of the balun when interfacing to the ADC input. The insertion loss should be considered so that the
signal at the balun output is within the specified input range of the ADC as described in the Converter Electrical
Characteristics as the specification V_IN.
d.c. Coupled Input
When d.c. coupling to the ADC08D1520 analog inputs, single-ended to differential conversion can be
accomplished with a high speed differential amplifier (LMH6555). Connecting the ADC08D1520 V_CMO pin to the
V_{CM_REF} pin of the LMH6555, via an appropriate buffer, will ensure that the common mode input voltage meets
the requirements for optimum performance of the ADC08D1520. The LMV321 was chosen to buffer V_CMO for its
low voltage operation and reasonable offset voltage. The output current from the ADC08D1520 V_CMO pin should
be limited to 100 μA.
Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and OR-
goes low. This output is active as long as accurate data on either or both of the buses would be outside the
range of 00h to FFh. Note that when the device is programmed to provide a second DCLK output, the OR
signals become DCLK2. Refer to REGISTER DESCRIPTION.
Full-Scale Input Range
As with all A/D Converters, the input range is determined by the value of the ADC's reference voltage. The
reference voltage of the ADC08D1520 is derived from an internal band-gap reference. The FSR pin controls the
effective reference voltage of the ADC08D1520 such that the differential full-scale input range at the analog
inputs is a normal amplitude with the FSR pin high, or a reduced amplitude with FSR pin low as defined by the
specification V_IN in the Converter Electrical Characteristics. Best SNR is obtained with FSR high.
THE CLOCK INPUTS
The ADC08D1520 has differential LVDS clock inputs, CLK+ and CLK-, which must be driven with an a.c.
coupled, differential clock signal. Although the ADC08D1520 is tested and its performance is ensured with a
differential 1.5 GHz clock, it typically will function well with input clock frequencies indicated in the Converter
Electrical Characteristics. The clock inputs are internally terminated and biased. The input clock signal must be
capacitive coupled to the clock pins as indicated in Figure 39.
Operation up to the sample rates indicated in the Converter Electrical Characteristics is typically possible if the
maximum ambient temperatures indicated are not exceeded. Operating at higher sample rates than indicated for
the given ambient temperature may result in reduced device reliability and product lifetime. This is because of the
higher power consumption and die temperatures at high sample rates. Important also for reliability is proper
thermal management. See Thermal Management.
C_couple
C_couple
CLK+
CLK-
ADC08D1520
Figure 39. Differential (LVDS) Input Clock Connection
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