ADC08D1520QML-SP Datasheet, PDF (12/59 Pages) Texas Instruments – ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

ADC08D1520QML-SP
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
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ADC08D1520 Converter Electrical Characteristics DC Parameters⁽¹⁾ (continued)
The following specifications apply after calibration for V_A = V_DR = +1.9V; OutV = 1.9V; V_IN FSR (a.c. coupled) = differential
870 mV_P-P; C_L = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, f_CLK = 1.5 GHz at 0.5 V_P-P with 50% duty cycle; V_BG =
Floating; Non-Extended Control Mode; SDR Mode; R_EXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω
Differential; 1:2 Output Demultiplex, duty cycle stabilizer on. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits T_A =
25°C, unless otherwise noted.⁽²⁾⁽³⁾
Parameter
Test Conditions
Notes Typ⁽⁴⁾ Min Max
Units
Sub-
groups
Phase Matching (I,Q)
f_IN = 1.0 GHz
<1
Crosstalk from I- Channel Aggressor = 1160 MHz F.S.
X-TALK (Aggressor) to Q- Channel Victim = 100 MHz F.S.
−66
(Victim)
Degree
dB
Crosstalk from Q- Channel Aggressor = 1160 MHz F.S.
X-TALK (Aggressor) to I- Channel Victim = 100 MHz F.S.
−66
dB
(Victim)
CLOCK INPUT CHARACTERISTICS
Sine Wave Clock
V_ID
Differential Clock Input
Level
Square Wave Clock
I_I
Input Current
C_IN
Input Capacitance
V_IN = 0 or V_IN = V_A
Differential
Each input to ground
.5
0.6
2.0
.5
0.6
2.0
±1
(8)
0.02
1.5
V_P-P
V_P-P
V_P-P
V_P-P
µA
pF
pF
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
DIGITAL CONTROL PIN CHARACTERISTICS
V_IH
Logic High Input Voltage
OutV, DCLK_RST, PD, PDQ, CAL
ECE, DRST_SEL
0.67 x
V_A
V
V_IL
Logic Low Input Voltage
OutV, DCLK_RST, PD, PDQ, CAL
0.33 x
V_A
V
V_IH
Logic High Input Voltage OutEdge, FSR, DES/SCS
0.77 x
V_A
V
OutEdge, FSR, ECE, DRST_SEL
V_IL
Logic Low Input Voltage
DES/SCS
(9)
C_IN
Input Capacitance
Each input to ground
(10)
1.2
0.23 x
V_A
V
0.23 x
V_A
V
pF
DIGITAL OUTPUT CHARACTERISTICS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
V_OD
LVDS Differential Output
Voltage
Change in LVDS Output
ΔV_{O DIFF} Swing Between Logic
Levels
Measured differentially,
OutV = V_A, V_BG = Floating
Measured differentially,
OutV = GND, V_BG = Floating
(11)
780
580
920
(11)
590
380
720
±1
mV_P-P
mV_P-P
mV_P-P
mV_P-P
mV
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
V_OS
Output Offset Voltage
V_BG = Floating (See Figure 2)
800
mV
V_OS
Output Offset Voltage
V_BG = V_A (See Figure 2)
(11) ₁₁₀₀
mV
ΔV_OS
Output Offset Voltage
Change Between Logic
Levels
±1
mV
(8) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(9) Refer to the Post Radiation Parameter Table
(10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
(11) Tying V_BG to the supply rail will increase the output offset voltage (V_OS) by 300mv (typical), as shown in the V_OS specification above.
Tying V_BG to the supply rail will also affect the differential LVDS output voltage (V_OD), causing it to increase by 30mV (typical).
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