CDCE72010 Datasheet, PDF (45/70 Pages) Texas Instruments – Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 9: CD Mode
SPI RAM
BIT
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
1
A1
Address 1
2
A2
Address 2
3
A3
Address 3
4
0 HOLDF1
Enables the Frequency Hold-Over Function 1 on 1, off 0
5
1 HOLDF2
Enables the Frequency Hold-Over Function 2 on 1, off 0
6
2 HOLD
3-State Charge Pump 0 - (equal to HOLD-Pin function)
7
3 HOLDTR
HOLD- Over
HOLD function always activated “1” (recommended for test purposes, only)
Triggered by analog PLL Lock detect outputs
If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated
If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated
8
4 HOLD_CNT0
9
5 HOLD_CNT1
HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by
(HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles.
For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles.
10
6 LOCKW 2
11
7 LOCKW 3
LOCK-DET
Extended Lock-detect window Bit 2 (Also refer to Reg 7 RAM Bits 0 and 1)
Extended Lock-detect window Bit 3 (Also refer to Reg 7 RAM Bits 0 and 1)
12
8
NOINV_RESHOL_IN
T
Chip CORE
When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)
When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted
13
9 DIVSYNC_DIS
Diagnostic: PLL
N/M Divider
When GTME = 0, this bit has no functionality, But when GTME = 1, then:
When set to 0, START-Signal is synchronized to N/M Divider Input Clocks
When set to 1, START-Sync N/M Divider in PLL are bypassed
14
10 START_BYPASS
Divider START When set to 0, START-Signal is synchronized to VCXO-Clock
DETERM-Block When set to 1, START-Sync Block is bypassed
15
11 INDET_BP
Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available
DETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks
16
12 PLL_LOCK_BP
Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state
DETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK
17
13 LOW_FD_FB_EN
Divider START
DETERM-Block
When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)
When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz,
stopped for VCXO/DIV_FB < ~600KHz
18
14 NPRESET_MDIV
PLL
When set to 0, M-Divider uses NHOLD1 as NPRESET
M/FB-Divider When set to 1, M-Divider NOT preseted by NHOLD1
19
15 BIAS_DIV_FB<0>
20
16 BIAS_DIV_FB<1>
Feedback
Divider
When BIAS_DIV_FB<1:0> =
00, No current reduction for FB-Divider
01, Current reduction for FB-Divider by about 20%
10, Current reduction for FB-Divider by about 30%
21
17 BIAS_DIV89<0>
22
18 BIAS_DIV89<1>
Output Divider
8 and 9
When BIAS_DIV89<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
23
19 AUXINVBB
24
20 DIS_AUX_Y9
AUX Buffer
If Set to 1 it Biases AUX Input Negative Pin with internal VCXOVBB voltage.
If Set to 1 AUX in input Mode Buffer is disabled. If Set to 0 it follows the
behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings.
25
21 PECL9HISWING
Output 9
High Output Voltage Swing in LVPECL Mode if set to 1
26
22 RESERVED
27
23 RESERVED
28
24 OUTBUF9CD2LX
29
25 OUTBUF9CD2LY
CD2 Low
Output Buffer 9 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
30
26 OUTBUF9CD2HX
31
27 OUTBUF9CD2HY
CD2 High
Output Buffer 9 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
POWER UP
CONDITION
1
0
0
1
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE72010
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