CDCE72010 Datasheet, PDF (2/70 Pages) Texas Instruments – Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

CDCE72010
SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com
DESCRIPTION
The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a
VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two
reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The
following relationship applies to the dividers:
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (R*M) / (P*N)
The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter
components. The PLL loop bandwidth and damping factor can be adjusted to meet different system
requirements.
The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports
frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user
definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The
built-in synchronization latches ensure that all outputs are synchronized for very low output skew.
All device settings, including output signaling, divider value selection, input selection, and many more, are
programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device
settings.
The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C.
PRI _I N
SEC_I N
PFD
Charge
Pump
VCXO/ VCO IN
PLL_LOCK
REF_SEL
POWER DOWN
RESET or HOLD
MODE_SEL
AUX_SEL
SPI_MISO
SPI_LE (CD1)
SPI_CLK (CD2)
SPI_MOSI (CD3)
Interface
& Control
EEPROM
Feedback
Divider
Output Divider 1
Output Divider 2
Output Divider 3
Output Divider 4
Output Divider 5
Output Divider 6
Output Divider 7
Output Divider 8
Auxiliary Input
Figure 1. High Level Block Diagram of the CDCE72010
U0P
U0N
U1P
U1N
U2P
U2N
U3P
U3N
U4P
U4N
U5P
U5N
U6P
U6N
U7P
U7N
U8P
U8N
U9P or AUX IN+
U9N or AUX IN–
2
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