TPS65520 Datasheet, PDF (44/61 Pages) Texas Instruments – POWER MANAGEMENT IC FOR DIGITAL STILL CAMERA

TPS65520
SLVS557A – MARCH 2005 – REVISED MARCH 2005
www.ti.com
• Test A: In the same way as Para mode, the TPS65520 allows access to the control registers. Unlike Para
mode, however, no parity check is performed. The parity judgment result is internally fixed to "OK" and the
contents of the shift register are sent to DOUT.
• Test 0: The contents of the control registers are copied to the shift register in synchronization with the TLD
input signal. After copying, a CLK input causes the control register value to appear at DOUT.
• Test 1: Prepare (latch) the data to be written to the user setup EEPROM. When Test 6 is performed
subsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks that
reference values from EEPROM will see the latched data, instead of the data stored in EEPROM.
• Test 2: The contents of the user setup EEPROM are copied to the shift register in synchronization with the
TLD input signal. After copying, a CLK input causes the value from the user setup EEPROM to appear at
DOUT.
• Test 3: The states of the protection functions are copied to the shift register in synchronization with the TLD
input signal. After copying, a CLK input causes the protection state value to appear at DOUT.
• Test 4: Prepare (latch) the data to be written to the trimming EEPROM. When Test 7 is performed
subsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks that
reference values from EEPROM will see the latched data, instead of the data stored in EEPROM.
• Test 5: The contents of the trimming EEPROM are copied to the shift register in synchronization with the
TLD input signal. After copying, a CLK input causes the value from the trimming EEPROM to appear at
DOUT.
• Test 6: Data is written to the user setup EEPROM.
• Test 7: Data is written to the trimming EEPROM.
• Test Mode Switching: Test A does not require a transition to a special mode. Its operation is the same as in
normal mode, except the difference in the DOUT output.
• Tests 0 to 7 require explicit mode switching using the Decoder shown in Figure 34. The Decoder uses the
three high-order bits in the shift register to change the mode. Table 4 shows the bit assignment.
Table 4. Bit Assignments
D[47]
*
0
0
0
0
1
1
1
1
D[46]
*
0
0
1
1
0
0
1
1
D[45]
*
0
1
0
1
0
1
0
1
MODE
Test A
Test 0
Test 1
Test 2
Test 3
Test 4
Test 5
Test 6
Test 7
• Information Read Mode: In Test mode, Tests 0, 2, 3, and 5 have a common function: copy some TPS65520
internal logic values to the shift register and read them from DOUT. Because their operations are nearly the
same, this section describes them together.
Figure 35 to Figure 38 shows the shift register configuration from input DIN and output DOUT as well as changes
in the shift register caused by a TLD input pulse.
47
44 43
DIN
000
DIN
000
40 39
36 35
32 31
28 27
24 23
20 19
16 15
12 11
08 07
04 03
0
DOUT
Dmax7 Dmax5 Dmax4 CH3−SWDmax3
CH7−SW
TLD pulse
Vout7
Vout5 Vout4
Vout3
Vout2
Vout1
Figure 35. Shift Register Configuration and Changes for Test 0
Dmax6
DOUT
Vout6B
LDOSW3
LDOSW5
LDO5Vo
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