TMS320VC5441 Datasheet, PDF (43/86 Pages) Texas Instruments – TMS320VC5441 Fixed-Point Digital Signal Processor

Functional Overview
BIT
NO.
15–12
11
10
9–6
5
BIT
NAME
Reserved
SOFT
FREE
PSC
TRB
Table 3–10. TCR Bit Description
FUNCTION
Register bit is reserved. Read 0, write has no effect.
Used in conjunction with the FREE bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
When FREE = 0 and SOFT = 0 the timer stops immediately.
When FREE = 0 and SOFT = 1, the timer stops when the counter decrements to 0.
Used in conjunction with the SOFT bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
When FREE = 0, the SOFT bit selects the timer mode.
When FREE = 1, the timer runs free regardless of the SOFT bit.
Timer prescalar counter, used only when PREMD = 0 (in TSCR register) and the prescaler is in direct mode.
Timer reload. When TRB is set, TIM is loaded with the value in the PRD register and the PSC field is loaded with
the value in the TDDR field (when prescalar is in direct mode). TRB is always read a 0.
Timer stop status.
4
TSS
Stops or starts the timer at reset. TSS is cleared and the timer starts timing.
0 = timer is started
1 = timer is stopped
Timer prescalar.
Case 1: When PREMD = 0, TDDR is a 4-bit reload prescalar. When PSC decrements to 0, PSC is loaded with
the contents of TDDR.
Case 2: When PREMD = 1,TDDR is an indirect prescalar, the contents in TDDR is used to specify the timer
prescalar.
3–0
TDDR
TDDR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PRESCALAR
0001h
0003h
0007h
000Fh
001Fh
003Fh
007Fh
00FFh
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
7FFFh
FFFFh
34 SPRS122E
December 1999 – Revised April 2002