TMS320VC5441 Datasheet, PDF (26/86 Pages) Texas Instruments – TMS320VC5441 Fixed-Point Digital Signal Processor

Memory Map with OVLY = 1
0000h
Page 0 Page 1 Page 2 Page 3
Functional Overview
MPDD
8000h
MDD0
or
MDD1
FFFFh
Data Memory
MPDD
MPDD
MPDD MPDD
MPCD0 MPCD1 MPCD2 MPCD3
Program Memory
Memory Map with OVLY = 0
0000h
Page 0 Page 1 Page 2 Page 3
MPDD
MPCD3 MPCD3 MPCD3 MPCD3
8000h
MDD0
or
MDD1
FFFFh
MPCD0
MPCD1
MPCD2 ^{ÒÒÒÒÒÒÒÒ}
Data Memory
NOTES: A. MPDD: local program/data memory in subsystem D
Program Memory
ÕÕÕÕ^reserved
B. MDD: local data memory in subsystem D. MDD is controlled by the data memory map register (DMMR).
DMMR=0, MDD0 is mapped in 8000h – FFFFh.
DMMR=1, MDD1 is mapped in 8000h – FFFFh.
C. MPCD: shared program memory in subsystems C and D
Figure 3–6. Subsystem D CPU Memory Map
Figure 3–7 shows the CPU data memory map. The lower 32K-word data memory location in all pages is the
overlay area. Program memory has overlay area over the lower 32K words on all pages as well.
The overlay areas refer to:
1. When OVLY = 1, the lower 32K words of data space are mapped to the lower 32K words of all program
pages in the memory map.
2. When OVLY = 0, the lower 32K words of data space are mapped only to the lower 32K words of data space
and the lower 32K words of program page 3 are mapped to the lower 32K words of all program pages.
December 1999 – Revised April 2002
SPRS122E
17