TMS320C30_08 Datasheet, PDF (43/54 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C30
DIGITAL SIGNAL PROCESSOR
SPRS032A – APRIL 1996 – REVISED JUNE 1997
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 26 occurs; otherwise, an additional delay of one clock cycle is
possible.
The “timing parameters for HOLD / HOLDA” table defines the timing parameters for the HOLD and HOLDA
signals. The numbers shown in Figure 26 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue until a second write is encountered.
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