TMS320C30_08 Datasheet, PDF (37/54 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C30
DIGITAL SIGNAL PROCESSOR
SPRS032A – APRIL 1996 – REVISED JUNE 1997
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 23
correspond with those in the NO. column of the table below.
timing parameters for IACK (see Note 6 and Figure 23)
’C30-27
’C30-33
’C30-40
’C30-50
NO.
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 td(H1H-IACKL) Delay time, H1 high to IACK low
13
10
9
7 ns
2 td(H1H-IACKH) Delay time, H1 high to IACK high
13
10
9
7 ns
NOTE 6: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of the pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
Fetch IACK
Instruction
H3
Decode IACK
Instruction
IACK Data
Read
H1
1
2
IACK
ADDR
Data
Figure 23. Timing for IACK
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