DAC5687IPZPR Datasheet, PDF (42/79 Pages) Texas Instruments – 16-BIT, 500 MSPS 2–8 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
www.ti.com
A type-four phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback
clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated
by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler div(1:0). The output of the prescaler
is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, and ÷8. The feedback clock is
selected by the registers sel(1:0), which is fed back to the PFD for synchronization to the input clock. The
feedback clock is also used for the data input rate, so the ratio of DAC output clock to feedback clock sets the
interpolation rate of the DAC5687. The PLLLOCK pin is an output indicating when the PLL has achieved lock. An
external RC low-pass PLL filter is provided by the user at pin LPF. See the Low-Pass Filter section for
filter-setting calculations. This is the only mode where the LPF filter applies.
CLK1
t_s(DATA)
t_h(DATA)
DA[15:0]
A₀
A₁
A₂
A₃
A_N
A_N+1
DB[15:0]
B₀
B₁
B₂
B₃
B_N
Figure 45. Dual-Bus Mode Timing Diagram (PLL Mode)
B_N+1
T0039-01
LPF
pll_div(1:0) PLLVDD
CLK1
CLK1C
CLK2
CLK2C
CLK
Buffer
CLK
Buffer
/1 00
PFD
Charge
Pump
VCO
/2 01
1
/4 10
/8 11
0
0
1
Lock
1 ´2
0 ´1
Data
Latch
f_DAC
00 /2
01
/2
10
11 /2
f_DAC/2 X2
f_DAC/4 X4
f_DAC/4 X4L
f_DAC/8 X8
Data
PLLLOCK
PLLVDD
DA[15:0]
DB[15:0]
interl
interp(1:0)
Figure 46. Clock Generation Architecture in PLL Mode
B0053-09
42
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