CC113L Datasheet, PDF (42/75 Pages) Texas Instruments – Value Line Receiver

CC113L
GDOx_CFG[5:0]
0 (0x00)
1 (0x01)
2 (0x02) - 3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08) - 9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10) - 27 (0x1B)
28 (0x1C)
29 (0x1D) – 38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
42 (0x2A)
43 (0x2B)
44 (0x2C) – 45 (0x2D)
46 (0x2E)
47 (0x2F)
48 (0x30)
49 (0x31)
50 (0x32)
51 (0x33)
52 (0x34)
53 (0x35)
54 (0x36)
55 (0x37)
56 (0x38)
57 (0x39)
58 (0x3A)
59 (0x3B)
60 (0x3C)
61 (0x3D)
62 (0x3E)
63 (0x3F)
Description
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-
asserts when RX FIFO is drained below the same threshold.
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the
end of packet is reached. De-asserts when the RX FIFO is empty.
Reserved - used for test.
Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
Reserved - used for test.
Asserts when sync word has been received, and de-asserts at the end of the packet. The pin will
also de-assert when a packet is discarded due to address or maximum length filtering or when the
radio enters RXFIFO_OVERFLOW state.
Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from
the RX FIFO.
Reserved - used for test.
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is
constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt
for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.
Data is set up on the falling edge by CC113L when GDOx_INV=0.
Serial Synchronous Data Output. Used for synchronous serial mode.
Serial Data Output. Used for asynchronous serial mode.
Carrier sense. High if RSSI level is above threshold. Cleared when entering IDLE mode.
CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.
Reserved - used for test.
LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an
external LNA in applications where the SLEEP state is used it is recommended to use
GDOx_CFGx=0x2F instead.
Reserved - used for test.
CLK_32k.
Reserved - used for test.
CHIP_RDYn.
Reserved - used for test.
XOSC_STABLE.
Reserved - used for test.
High impedance (3-state).
HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA
CLK_XOSC/1
CLK_XOSC/1.5
CLK_XOSC/2
CLK_XOSC/3
CLK_XOSC/4
CLK_XOSC/6
Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an
output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins,
the other two GDO pins must be configured to values less than 0x30. The
GDO0 default value is CLK_XOSC/192.
To optimize RF performance, these signals should not be used while the radio is
in RX mode.
CLK_XOSC/8
CLK_XOSC/12
CLK_XOSC/16
CLK_XOSC/24
CLK_XOSC/32
CLK_XOSC/48
CLK_XOSC/64
CLK_XOSC/96
CLK_XOSC/128
CLK_XOSC/192
Table 29: GDOx Signal Selection (x = 0, 1, or 2)
SWRS108A
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