CC113L Datasheet, PDF (23/75 Pages) Texas Instruments – Value Line Receiver

CC113L
Bits Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4 STATE[2:0]
Indicates the current main state machine mode
Value State
Description
000 IDLE
IDLE state (Also reported for some transitional
states instead of SETTLING or CALIBRATE)
001 RX
Receive mode
010 Reserved
011 Reserved
100 CALIBRATE
Frequency synthesizer calibration is running
101 SETTLING
PLL is settling
110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any useful
data, then flush the FIFO with SFRX
111 Reserved
3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO
Table 16: Status Byte Summary
10.2 Register Access
The configuration registers on the CC113L are
located on SPI addresses from 0x00 to 0x2E.
Table 31 on page 46 lists all configuration
registers. It is highly recommended to use
SmartRF Studio [4] to generate optimum
register settings. The detailed description of
each register is found in Section 26.1 and
Section 26.2, starting on page 49. All
configuration registers can be both written to
and read. The R/W¯ bit controls if the register
should be written to or read. When writing to
registers, the status byte is sent on the SO pin
each time a header byte or data byte is
transmitted on the SI pin. When reading from
registers, the status byte is sent on the SO pin
each time a header byte is transmitted on the
SI pin.
10.3 SPI Read
When reading register fields over the SPI
interface while the register fields are updated
by the radio hardware (e.g. MARCSTATE or
RXBYTES), there is a small, but finite,
probability that a single read from the register
10.4 Command Strobes
Command Strobes may be viewed as single
byte instructions to CC113L. By addressing a
command strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable calibration etc. The 8 command
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit (B) in the header byte. The address
bits (A₅ - A₀) set the start address in an
internal address counter. This counter is
incremented by one each new byte (every 8
clock pulses). The burst access is either a
read or a write access and must be terminated
by setting CSn high.
For register addresses in the range
0x30 - 0x3D, the burst bit is used to select
between status registers when burst bit is one,
and command strobes when burst bit is zero.
See more in Section 10.3 below. Because of
this, burst access is not available for status
registers and they must be accessed one at a
time. The status registers can only be read.
is being corrupt. As an example, the
probability of any single read from RXBYTES
being corrupt, assuming the maximum data
rate is used, is approximately 80 ppm. Refer to
the CC113L Errata Notes [3] for more details.
strobes are listed in Table 30
on page 45.
SWRS108A
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