ADS61B23 Datasheet, PDF (41/51 Pages) Texas Instruments – 12-BIT, 80-MSPS ADC WITH BUFFERED ANALOG INPUTS

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ADS61B23
SLAS582 – FEBRUARY 2008
CLKOUTM
CLKOUTP
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
Sample N
Sample N+1
Figure 44. DDR LVDS Interface
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistors available are – 300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistance. This results in eight effective terminations from open (no
termination) to 65 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 45 and Figure 46 compare the LVDS eye diagrams without and with internal termination (100 Ω).
With internal termination, the eye looks clean even with 10 pF load capacitance (from each output pin to ground).
The terminations is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 12).
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