ADS61B23 Datasheet, PDF (25/51 Pages) Texas Instruments – 12-BIT, 80-MSPS ADC WITH BUFFERED ANALOG INPUTS

ADS61B23
www.ti.com
SLAS582 – FEBRUARY 2008
TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 80 MSPS, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input (1.8 Vpp) , internal reference mode, 0 dB gain,
unless otherwise noted.
FFT for 20 MHz INPUT SIGNAL
0
SFDR = 81 dBc
−20 ^{SINAD = 69.7 dBFS}
SNR = 70 dBFS
−40 ^{THD = 80 dBc}
−60
−80
−100
−120
−140
−160
0
10
20
30
f − Frequency − MHz
Figure 9.
40
G001
INTERMODULATION DISTORTION
0
−20
f_IN1 = 50.1 MHz, –7 dBFS
f_IN2 = 46.1 MHz, –7 dBFS
2-Tone IMD = –85.31 dBFS
−40 ^{SFDR = –90.8 dBFS}
−60
−80
−100
−120
−140
−160
0
10
20
30
f − Frequency − MHz
Figure 11.
40
G003
SNR vs. INPUT FREQUENCY
FOR 1.8Vpp and 1Vpp INPUT SIGNAL (AT 0 dB GAIN)
72
71
70
1 V_PP
69
68
1.8 V_PP
67
66
65
0
20 40 60 80 100 120 140 160 180 200 220
f_IN − Input Frequency − MHz
G005
Figure 13.
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 81.3 dBc
−20 ^{SINAD = 69.3 dBFS}
SNR = 69.6 dBFS
−40 ^{THD = 78.9 dBc}
−60
−80
−100
−120
−140
−160
0
10
20
30
f − Frequency − MHz
Figure 10.
40
G002
SFDR vs. INPUT FREQUENCY
FOR 1.8Vpp and 1Vpp INPUT SIGNAL (AT 0 dB GAIN)
92
88
84
1 V_PP
80
76
72
68
1.8 V_PP
64
60
0
20 40 60 80 100 120 140 160 180 200 220
f_IN − Input Frequency − MHz
G004
Figure 12.
100
95
90
85
80
75
70
65
60
55
50
0
SFDR ACROSS COARSE GAIN
FOR 1.8Vpp and 1Vpp INPUT SIGNAL
1 V_PP, 3.5 dB
1 V_PP, 0 dB
1.8 V_PP, 3.5 dB
1.8 V_PP, 0 dB
20 40 60 80 100 120 140 160 180 200 220
f_IN − Input Frequency − MHz
G006
Figure 14.
Copyright © 2008, Texas Instruments Incorporated
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