TMS320C6413_08 Datasheet, PDF (40/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Interrupt Sources and Interrupt Selector
Table 2−21. TMS320C6413/C6410 EDMA Channel Synchronization Events^† (Continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
41
AREVTE1
McASP1 receive even event
42
AREVTO1
McASP1 receive odd event
43
AREVT1
McASP1 receive event
44
ICREVT0
I2C0 receive event
45
ICXEVT0
I2C0 transmit event
46
ICREVT1
I2C1 receive event
47
ICXEVT1
I2C1 transmit event
48
GPINT8
GP0 event 8
49
GPINT9
GP0 event 9
50
GPINT10
GP0 event 10
51
GPINT11
GP0 event 11
52
GPINT12
GP0 event 12
53
GPINT13
GP0 event 13
54
GPINT14
GP0 event 14
55
GPINT15
GP0 event 15
56−63
–
None
† _{In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer}
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
2.8 Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 2−22. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 2−22. The interrupt source for interrupts 4−15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
40 _SPRS247F
April 2004 − Revised January 2006