VCA8500 Datasheet, PDF (4/15 Pages) Texas Instruments – 8-Channel, Ultra-Low Power Variable Gain Amplifier with Low-Noise Pre-Amp

VCA8500
SBOS390 – JANUARY 2008
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T_A = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (≤ 1µF) input configuration to the preamp
(LNA), f_IN = 5MHz, V_CNTL = 1.0V, VCA output is 2V_PP differential, R_LOAD = 1kΩ on each output to ground, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VCA8500
MIN
TYP
MAX
UNIT
TEST
LEVEL ⁽¹⁾
CW SIGNAL PATH
Output transconductance (V/I)
15
mA/V
I_OUT-CW
I_OUT-DC
V_CMO
V_Cout
C_OUT
Z_OUT
THD_CW
Dynamic CW output current
Static CW output current
Output common-mode voltage
Output compliance range
Output capacitance
Output impedance
Harmonic distortion
Signal current
Symmetric around V_CMO
HD2
HD3
TBD
2.4 (±1.2)
0.9
2.5
±0.5
< 10
50
TBD
TBD
TBD
mA_PP
mA
V_DC
V
pF
kΩ
dBc
dBc
e_N, RTI
Input voltage noise, CW mode
Signal-dependent noise (RTO)
At f = 2MHz
At 2kHz offset from
2MHz CW carrier
1.1
nV/√Hz
+2
dB
At 2kHz offset from
5MHz CW carrier
+2
dB
Output noise correlation factor
Summing of eight channels
[compared to ideal 0dB (SNR)]
0.6
dB
FILTER
LPF
Low-pass filter (second-order)
–3dB point, V_CNTL = 1.2V
Tolerance
10
MHz
±10
±15
%
Group delay (variation)
TBD
ns
Gain flatness
–1dB point
TBD
MHz
HPF
High-pass filter (first-order, due to
internal ac coupling)
–3dB point, V_CNTL = 1.2V
150
kHz
ACCURACY
Gain error (VCA)⁽³⁾
Gain range
Gain slope
Gain matching, channel-to-channel
Gain, PGA
V_CNTL = 0V to 1.2V
V_CNTL = 0V to 1.2V
V_CNTL = 0V to 1.2V
V_CNTL = 0V to 1.2V
Selectable through SDI
TBD
±0.25
45
37.5
±0.5
20, 25, 27,
30
±0.5
TBD
±1.5
dB
dB
dB/V
dB
dB
V_OS
Output offset voltage
tab Differential
–25
±5
+25
mV
tab Common-mode
–50
±25
+50
mV
GAIN CONTROL INTERFACE
V_CNTL
Input voltage range
Input resistance
Gain range = 45dB
0 to 1.2
V
25
kΩ
Response time
0.75
µs
Gain control bandwidth
DIGITAL INPUTS (SDI)⁽⁴⁾⁽⁵⁾
V_CNTL= 0V to 1.2V step;
to 90% Signal Level
(PD, DIN, DOUT, CLK, RST)
1.5
MHz
V_IH
V_IH, High-level input voltage
V_IL
V_IL, Low-level input voltage
I_IN
Input current
f_CLK
Clock frequency
Input resistance
2.0
VD
V
0
0.8
V
±10
µA
10k
20M
Hz
1
MΩ
Input capacitance
5
pF
(3) Compared to a standard curve. This is also Gain Error vs V_CONTROL.
(4) Parameters ensured by design; not production tested.
(5) Internal pull-up/pull-down resistors.
4
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