VCA8500 Datasheet, PDF (12/15 Pages) Texas Instruments – 8-Channel, Ultra-Low Power Variable Gain Amplifier with Low-Noise Pre-Amp

VCA8500
SBOS390 – JANUARY 2008
www.ti.com
WRITE/READ TIMING
• All writes and reads are five bytes at a time. Each byte consists of 8 bits, for a total instruction set of 40 bits.
• Data are latched on the falling edge of CLK.
• Separate write (DIN) and read data (DOUT) lines.
• Reads follow the same bitstream pattern seen in the write cycle.
• Reads extract data from the FIFO buffer, not the latched register.
• DOUT data are continuously available and do not need to be enabled with a read cycle. Selecting a read
cycle in the control register only prevents latching of data. The control register remains latched.
• The Reset pin (RS) must be low in order to allow the register to update with new data. RST can be held low
permanently. To initiate a reset cycle, pull the RST pin high for at least 100ns.
WRITE CYCLE TIMING
RST (Low)
CLK
DIN
t₂
t₃
t₅
t₄
t₁
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
NOTE: Figure shows timing example for one data byte. A full register update cycle requires all five bytes (that is, 40 bits).
PARAMETER
t₁
t₂
t₃
t₄
t₅
SERIAL PORT TIMING TABLE
DESCRIPTION
Serial CLK Period
Serial CLK HIGH Time
Serial CLK LOW Time
Data Hold Time
Data Setup Time
Reset Pulse (L - H - L)
MIN
TYP
MAX
100
40
40
5
5
100
UNIT
ns
ns
ns
ns
ns
ns
12
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