TLC540I Datasheet, PDF (4/11 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS

TLC540I, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A – OCTOBER 1983 – REVISED MARCH 1995
recommended operating conditions
TLC540
MIN NOM
MAX
TLC541
MIN NOM
UNIT
MAX
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref– (see Note 2)
Differential reference voltage, Vref+ – Vref– (see Note 2)
Analog input voltage (see Note 2)
High-level control input voltage, VIH
Low-level control input voltage, VIL
Setup time, address bits at data input before I/O CLOCK↑,
tsu(A)
Hold time, address bits after I/O CLOCK↑, th(A)
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 3)
4.75
2.5
– 0.1
1
0
2
200
0
3
5
5.5
VCC VCC + 0.1
0
2.5
VCC VCC + 0.2
VCC
0.8
4.75
5
5.5 V
2.5 VCC VCC + 0.1 V
– 0.1
0
2.5 V
1 VCC VCC + 0.2 V
0
VCC V
2
V
0.8 V
400
ns
0
ns
System
3
clock
cycles
CS high during conversion, twH(CS)
System
36
36
clock
cycles
I/O CLOCK frequency, fclock(I/O)
0
2.048
0
1.1 MHz
Pulse duration, SYSTEM CLOCK frequency, fclock(SYS)
fclock(I/O)
4 fclock(I/O)
2.1 MHz
Pulse duration, SYSTEM CLOCK high, twH(SYS)
110
210
MHz
Pulse duration, SYSTEM CLOCK low, twL(SYS)
100
190
MHz
Pulse duration, I/O clock high, twH(I/O)
200
404
ns
Pulse duration, I/O clock low, twL(I/O)
200
404
ns
Clock transition time
(see Note 4)
System
I/O
fclock(SYS) ≤ 1048 kHz
fclock(SYS) > 1048 kHz
fclock(I/O) ≤ 525 kHz
fclock(I/O) > 525 kHz
30
30
20
20
ns
100
100
40
40
Operating free-air temperature, TA TLC540I, TLC541I
– 40
85
– 40
85 °C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all “1”s (11111111), while input voltages less than that applied
to REF– convert as all “0”s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also,
the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at CS, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until
the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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