THS7373_10 Datasheet, PDF (4/50 Pages) Texas Instruments – 4-Channel Video Amplifier with 1-SD and 3-HD Sixth-Order Filters and 6-dB Gain

THS7373
SBOS506 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: V_S+ = +3.3 V (continued)
At T_A = +25°C, R_L = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7373
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AC PERFORMANCE (HD CHANNELS) (continued)
f = 30 MHz, Filter mode
1.4
Output impedance
f = 30 MHz, Bypass mode
1
Disabled
1.8 || 3
Return loss
f = 30 MHz, Filter mode
41
f = 1 MHz, HD to CVBS channel
–78
Crosstalk
f = 1 MHz, CVBS to HD channels
–85
f = 1 MHz, HD to HD channels
–78
DC PERFORMANCE
Biased output voltage
Input voltage range
V_IN = 0 V, CVBS channel
V_IN = 0 V, HD channels
DC input, limited by output
200
300
400
200
300
400
–0.1/1.46
Sync-tip clamp charge current
Input impedance
V_IN = –0.1 V, CVBS channel
V_IN = –0.1 V, HD channels
140
200
280
400
800 || 2
OUTPUT CHARACTERISTICS
High output voltage swing
Low output voltage swing
Output current (sourcing)
Output current (sinking)
POWER SUPPLY
R_L = 150 Ω to +1.65 V
R_L = 150 Ω to GND
R_L = 75 Ω to +1.65 V
R_L = 75 Ω to GND
R_L = 150 Ω to +1.65 V (V_IN = –0.2 V)
R_L = 150 Ω to GND (V_IN = –0.2 V)
R_L = 75 Ω to +1.65 V (V_IN = –0.2 V)
R_L = 75 Ω to GND (V_IN = –0.2 V)
R_L = 10 Ω to +1.65 V
R_L = 10 Ω to +1.65 V
3.15
2.85
3.1
3.1
3
0.04
0.03
0.1
0.1
0.05
80
70
Operating voltage
2.6
3.3
5.5
Total quiescent current, no load
V_IN = 0 V, all channels on
13.4
16.2
21
V_IN = 0 V, all channels off, V_DISABLE = 3 V
0.1
10
Power-supply rejection ratio
(PSRR)
At dc
52
LOGIC CHARACTERISTICS⁽³⁾
V_IH
V_IL
I_IH
I_IL
Disable time
Disabled or Bypass mode
Enabled or Filter mode
Applied voltage = 3.3 V
Applied voltage = 0 V
2
1.8
0.7
0.65
0.2
0.2
150
Enable time
150
Bypass/filter switch time
15
TEST
UNITS LEVEL⁽¹⁾
Ω
C
Ω
C
kΩ || pF
C
dB
C
dB
C
dB
C
dB
C
mV
A
mV
A
V
C
μA
A
μA
A
kΩ || pF
C
V
C
V
A
V
C
V
C
V
C
V
A
V
C
V
C
mA
C
mA
C
V
B
mA
A
μA
A
dB
C
V
A
V
A
μA
C
μA
C
ns
C
ns
C
ns
C
(3) The logic input pins should not be left floating. They must be connected to logic low (or GND) or logic high (or V_S+).
4
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