SN74V3640 Datasheet, PDF (4/50 Pages) Texas Instruments – 1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Partial Reset (PRS) Master Reset (MRS)
Write Clock (WCLK)
Write Enable (WEN)
Load (LD)
(×36, ×18, ×9) Data In (D0–Dn)
Serial Enable (SEN)
First-Word Fall-Through or Serial Input
(FWFT/SI)
Full Flag or Input Ready (FF/IR)
Programmable Almost-Full Flag (PAF)
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
(×36, ×18, ×9) Data Out (Q0–Qn)
Retransmit (RT)
Empty Flag or Output Ready (EF/OR)
Programmable Almost-Empty Flag (PAE)
Half-Full Flag (HF)
Big Endian/Little Endian (BE)
Interspersed/
Noninterspersed Parity (IP)
Input Width (IW)
Bus Output Width (OW)
Matching
(BM)
Figure 1. Single-Device-Configuration Signal Flow
description (continued)
These FIFOs have five flag pins: empty flag or output ready (EF/OR), full flag or input ready (FF/IR), half-full
flag (HF), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF). The EF and FF
functions are selected in standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE, and
PAF always are available for use, regardless of timing mode.
PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets
determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset
settings also are provided, so that PAE can be set to switch at a predefined number of locations from the empty
boundary. The PAF threshold also can be set at similar predefined values from the full boundary. The default
offset values are set during master reset by the state of the FSEL0, FSEL1, and LD.
For serial programming, SEN, together with LD, loads the offset registers via the serial input (SI) on each rising
edge of WCLK. For parallel programming, WEN, together with LD, loads the offset registers via Dn on each
rising edge of WCLK. REN, together with LD, can read the offsets in parallel from Qn on each rising edge of
RCLK, regardless of whether serial parallel offset loading has been selected.
During master reset (MRS), the read and write pointers are set to the first location of the FIFO. The FWFT pin
selects standard mode or FWFT mode.
Partial reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing
mode, programmable-flag programming method, and default or programmed offset settings existing before
partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS
is useful for resetting a device in mid-operation, when reprogramming programmable flags would be
undesirable.
Also, the timing modes of PAE and PAF outputs can be selected. Timing modes can be set as either
asynchronous or synchronous for PAE and PAF.
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