SN74V3640 Datasheet, PDF (1/50 Pages) Texas Instruments – 1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
D Choice of Memory Organizations
– SN74V3640 – 1024 × 36 Bit
– SN74V3650 – 2048 × 36 Bit
– SN74V3660 – 4096 × 36 Bit
– SN74V3670 – 8192 × 36 Bit
– SN74V3680 – 16384 × 36 Bit
– SN74V3690 – 32768 × 36 Bit
D 166-MHz Operation (6-ns Read/Write Cycle
Time)
D User-Selectable Input- and Output-Port Bus
Sizing
– ×36 in to ×36 out
– ×36 in to ×18 out
– ×36 in to ×9 out
– ×18 in to ×36 out
– ×9 in to ×36 out
D Big-Endian/Little-Endian User-Selectable
Byte Representation
D 5-V-Tolerant Inputs
D Fixed, Low, First-Word Latency
D Zero-Latency Retransmit
D Master Reset Clears Entire FIFO
D Partial Reset Clears Data, But Retains
Programmable Settings
D Empty, Full, and Half-Full Flags Signal FIFO
Status
D Programmable Almost-Empty and
Almost-Full Flags; Each Flag Can Default to
One of Eight Preselected Offsets
D Selectable Synchronous/Asynchronous
Timing Modes for Almost-Empty and
Almost-Full Flags
D Program Programmable Flags by Either
Serial or Parallel Means
D Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR and IR Flags)
D Output Enable Puts Data Outputs in
High-Impedance State
D Easily Expandable in Depth and Width
D Independent Read and Write Clocks Permit
Reading and Writing Simultaneously
D High-Performance Submicron CMOS
Technology
D Available in 128-Pin Thin Quad Flat Pack
(TQFP)
description
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally
deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible
bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:
D Flexible ×36/×18/×9 bus matching on both read and write ports
D The period required by the retransmit operation is fixed and short.
D The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can
be read, is fixed and short.
D High-density offerings up to 1 Mbit
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,
telecommunications, data communications, and other applications that need to buffer large amounts of data
and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or
9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus
matching (BM) during the master-reset cycle.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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