CDC516 Datasheet, PDF (4/11 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
Terminal Functions
TERMINAL
NAME
NO.
CLK
12
TYPE
I
FBIN
37
I
1G
9
I
2G
16
I
3G
33
I
4G
40
I
FBOUT
35
O
1Y(0:3)
2, 3, 6, 7
O
2Y(0:3) 18, 19, 22, 26 O
3Y(0:3) 31, 30, 27, 26 O
4Y(0:3) 47, 46, 43, 42 O
AVCC
11, 38
Power
AGND
VCC
GND
13, 14, 36 Ground
1, 8, 17, 24,
25, 32, 41, 48
Power
4, 5, 10, 15,
20, 21, 28, 29, Ground
34, 39, 44, 45
DESCRIPTION
Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
4
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265