CDC516 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to Four Banks
of Four Outputs
D Separate Output Enable for Each Output
Bank
D External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D No External RC Network Required
D Operates at 3.3-V V_CC
D Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
description
The CDC516 is a high-performance, low-skew,
low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the feedback output
(FBOUT) to the clock (CLK) input signal. It is
specifically designed for use with synchronous
DRAMs. The CDC516 operates at 3.3-V V_CC and
is designed to drive up to five clock loads per
output.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.
DGG PACKAGE
(TOP VIEW)
V_CC 1
1Y0 2
1Y1 3
GND 4
GND 5
1Y2 6
1Y3 7
V_CC 8
1G 9
GND 10
AV_CC 11
CLK 12
AGND 13
AGND 14
GND 15
2G 16
V_CC 17
2Y0 18
2Y1 19
GND 20
GND 21
2Y2 22
2Y3 23
V_CC 24
48 V_CC
47 4Y0
46 4Y1
45 GND
44 GND
43 4Y2
42 4Y3
41 V_CC
40 4G
39 GND
38 AV_CC
37 FBIN
36 AGND
35 FBOUT
34 GND
33 3G
32 V_CC
31 3Y0
30 3Y1
29 GND
28 GND
27 3Y2
26 3Y3
25 V_CC
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV_CC to ground.
The CDC516 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
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