CDC305 Datasheet, PDF (4/7 Pages) Texas Instruments – OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax‡
tPLH
tPHL
tPLH
tPHL
tsk(o)
FROM
(INPUT)
CLK
PRE or CLR
CLK
tsk(p)
CLK
tr
tf
† _{All typical values are at VCC = 5 V, TA = 25°C.}
‡ _{fmax minimum values are at CL = 0 to 30 pF.}
TO
(OUTPUT)
Q, Q
Q, Q
Q
Q
Q1– Q8
Q1, Q8
Q2 – Q7
TEST CONDITIONS
RL = 500 Ω, CL = 50 pF
RL = 500 Ω, CL = 50 pF
RL = 500 Ω, CL = 10 pF to 30 pF,
See Figure 2
RL = 500 Ω, CL = 10 pF to 30 pF
MIN TYP† MAX UNIT
80
MHz
2
6
9
ns
2
6
9
3
7
12
ns
3
7
12
1
1 ns
1.5
1.5
ns
2
4.5 ns
3.5 ns
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
Test Point
RL
LOAD CIRCUIT
CLR
or
PRE
CLK
1.3 V
tsu
tw
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
tPLH
tPHL
0.3 V
VOH
Q
1.3 V
1.3 V
VOL
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
4
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