CDC305 Datasheet, PDF (1/7 Pages) Texas Instruments – OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
D Replaces SN74AS305
D Maximum Output Skew of 1 ns
D Maximum Pulse Skew of 1ns
D TTL-Compatible Inputs and Outputs
D Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
D Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
description
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Q3 1
Q4 2
GND 3
GND 4
GND 5
Q5 6
Q6 7
Q7 8
16 Q2
15 Q1
14 CLR
13 V_CC
12 V_CC
11 CLK
10 PRE
9 Q8
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters t_sk(o) and t_sk(p) to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR PRE CLK Q1– Q4 Q5– Q8
L
H
X
L
H
H
L
X
H
L
L
L
X
L†
L†
H
H
L
Q0
Q0
H
H
↑
Q0
Q0
† _{This configuration does not persist when}
PRE or CLR returns to its inactive (high)
level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
1