CD54HC03_07 Datasheet, PDF (4/13 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
DC Electrical Specifications (Continued)
PARAMETER
Low Level Output
Voltage CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
TEST
CONDITIONS
25^oC
SYMBOL
V_OL
V_I (V)
V_IH or
V_IL
I_O (mA) V_CC (V) MIN
0.02
4.5
-
4
4.5
-
TYP MAX
- 0.1
- 0.26
I_I
V_CC
-
and
GND
I_CC
V_CC or
0
GND
∆I_CC
V_CC
-
(Note 4) - 2.1
5.5
-
±0.1
5.5
-
-
2
4.5 to - 100 360
5.5
-40^oC TO 85^oC
MIN MAX
-
0.1
-
0.33
-
±1
-
20
-
450
NOTE:
4. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
-
0.1
V
-
0.4
V
-
±1
µA
-
40
µA
-
490
µA
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nB
1
NOTE: Unit Load is ∆I_CC limit
tions table, e.g., 360µA max at
specified
25^oC.
in
DC
Electrical
Specifica-
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t_PLH, t_PHL C_L = 50pF
2
-
- 100
-
125
-
150
ns
4.5 -
-
20
-
25
-
30
ns
6
-
- 17
-
21
-
26
ns
Propagation Delay, Data Input to t_PLH, t_PHL C_L = 15pF
5
-8
-
-
-
-
-
ns
Output Y
Transition Times (Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
- 75
-
4.5 -
-
15
-
95
18
110
ns
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
C_I
C_PD
-
-
-
-
10
-
10
-
10
pF
-
5
- 6.4 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Input to Output (Figure 1)
t_PLH, t_PHL C_L = 50pF
4.5 -
-
24
-
30
-
36
ns
Propagation Delay, Data Input to t_PLH, t_PHL C_L = 15pF
5
-9
-
-
-
-
-
ns
Output Y
Transition Times (Figure 1)
t_TLH, t_THL C_L = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
C_I
-
-
-
-
10
-
10
-
10
pF
4