CD54HC03_07 Datasheet, PDF (3/13 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

CD54HC03, CD74HC03, CD54HCT, CD74HCT03
Absolute Maximum Ratings
DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC Drain Current, per Output, I_O
For -0.5V < V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA
DC V_CC or Ground Current, I_{CC or} I_GND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3)
θ_JA (^oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature (Hermetic Package or Die) . . . 175^oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150^oC
Maximum Storage Temperature Range . . . . . . . . . .-65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300^oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T_A) . . . . . . . . . . . . . . . . . . . . . -55^oC to 125^oC
Supply Voltage Range, V_CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V_I, V_O . . . . . . . . . . . . . . . . . 0V to V_CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
SYMBOL
TEST
CONDITIONS
25^oC
V_I (V) I_O (mA) V_CC (V) MIN TYP MAX
V_IH
-
-
V_IL
-
-
V_OL
V_IH or 0.02
V_IL
0.02
0.02
-
4
5.2
I_I
V_CC or
-
GND
I_CC
V_CC or
0
GND
2
1.5 -
-
4.5 3.15 -
-
6
4.2 -
-
2
-
- 0.5
4.5
-
- 1.35
6
-
- 1.8
2
-
- 0.1
4.5
-
- 0.1
6
-
- 0.1
-
-
-
-
4.5
-
- 0.26
6
-
- 0.26
6
-
- ±0.1
6
-
-
2
V_IH
-
V_IL
-
-
4.5 to 2
-
-
5.5
-
4.5 to -
- 0.8
5.5
-40^oC TO 85^oC
MIN MAX
1.5
-
3.15
-
4.2
-
-
0.5
-
1.35
-
1.8
-
0.1
-
0.1
-
0.1
-
-
-
0.33
-
0.33
-
±1
-
20
2
-
-
0.8
-55^oC TO 125^oC
MIN MAX UNITS
1.5
-
V
3.15
-
V
4.2
-
V
-
0.5
V
-
1.35
V
-
1.8
V
-
0.1
V
-
0.1
V
-
0.1
V
-
-
V
-
0.4
V
-
0.4
V
-
±1
µA
-
40
µA
2
-
V
-
0.8
V
3