CD54AC112 Datasheet, PDF (4/10 Pages) Intersil Corporation – Dual “J-K” Flip-Flop with Set and Reset

CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
timing requirements over recommended operating free-air temperature range, V_CC = 1.5 V (unless
otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↓
th
Hold time, after CLK↓
trec
Recovery time, before CLK↓
CLK high or low
CLR or PRE low
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
8
63
56
50
0
31
–40°C to
85°C
MIN MAX
9
55
49
44
0
27
UNIT
MHz
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↓
th
Hold time, after CLK↓
trec
Recovery time, before CLK↓
CLK high or low
CLR or PRE low
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
71
7
6.3
5.6
0
3.5
–40°C to
85°C
MIN MAX
81
6
5.5
4.9
0
3..1
UNIT
MHz
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature0 range, V_CC = 5 V ± 0.5 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↓
th
Hold time, after CLK↓
trec
Recovery time, before CLK↓
CLK high or low
CLR or PRE low
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
100
5
4.5
4
0
2.5
–40°C to
85°C
MIN MAX
114
4.4
3.9
3.5
0
2.2
UNIT
MHz
ns
ns
ns
ns
4
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