BQ24705 Datasheet, PDF (4/30 Pages) Texas Instruments – Host-Controlled Multi-Chemistry Battery Charger With Low Input Power Detect

bq24705
SLUS779 – DECEMBER 2007
www.ti.com
Table 1. TERMINAL FUNCTIONS – 24-PIN QFN
TERMINAL
DESCRIPTION
NAME
NO.
PVCC
IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
1 and source of reverse-blocking power P-channel MOSFET. Place a 1-µF ceramic capacitor from PVCC to PGND pin
close to the IC.
CHGEN
2 Charge enable active-low logic input. LO enables charge. HI disables charge.
ACN
Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
3 for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering.
ACP
4 Adapter current sense resistor, positive input. (See comments with ACN description)
ACDET
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
5
input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The I_ADAPT
current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV, disables
charge and ACDRV when ACDET > 3.1 V. ACOV does not latch
ACSET
Adapter current set input. The voltage ratio of ACSET voltage versus VREF voltage programs the input current
6 regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VREF
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin.
AGND
7
Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power
pad underneath the IC.
VREF
8
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation.
VADJ
Charge voltage set input. The voltage ratio of VADJ voltage versus VREF voltage programs the battery voltage
9 regulation set-point. Program by connecting a resistor divider from VREF to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ. VADJ connected to REGN programs the default of 4.2 V per cell.
ACGOOD
Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed
10 threshold, OR input current is greater than 1.25 A with 10-mΩ sense resistor. Connect a 10-kΩ pullup resistor from
ACGOOD pin to pullup supply rail.
ISYNSET
Synchronous mode voltage set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent
11 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor current.
Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).
IADAPT
12
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
SRSET
Charge current set input. The voltage ratio of SRSET voltage versus VREF voltage programs the charge current
13 regulation set-point. Program by connecting a resistor divider from VREF to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
BAT
14 pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter
high-frequency noise.
SRN
Charge current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND
15 for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering.
SRP
16 Charge current sense resistor, positive input. (See comments for SRN.)
CELLS
17 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
DPMDET
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
18 current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a
different pullup-supply rail.
PGND
19
Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input
and output capacitors of the charger. Only connect to AGND through the power pad underneath the IC.
LODRV
20 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
REGN
21
PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET
PH
22 drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from from PH to
BTST.
HIDRV
23 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST
24
PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a
small bootstrap Schottky diode from REGN to BTST.
4
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